SOVA sharing during LDPC global iteration

ABSTRACT

Decoding is performed on input data to obtain first decoded data using a first error correction decoder. If decoding by a second error correction decoder on the first decoded data fails, decoding is performed using an output of the second decoder and using the first decoder. A reservation request is sent from the second error correction decoder to a memory prior to completion of the decoding on the first decoded data. Space is reserved in the memory in response to receiving the reservation request from the second decoder.

CROSS REFERENCE TO OTHER APPLICATIONS

This application is a continuation of co-pending U.S. patent applicationSer. No. 12/587,999, entitled SOVA SHARING DURING LDPC GLOBAL ITERATIONfiled Oct. 14, 2009 which is incorporated herein by reference for allpurposes, which claims priority to U.S. Provisional Application No.61/196,633, entitled SOVA SHARING DURING LDPC GLOBAL ITERATION filedOct. 20, 2008 which is incorporated herein by reference for allpurposes.

BACKGROUND OF THE INVENTION

In some error correction systems, encoded data is first decoded by aViterbi decoder and then by a low-density parity-check (LDPC) decoder.In some cases, the encoded data fails LDPC decoding (e.g., because thereis a significant amount of noise in the encoded data being processed).In such cases, Viterbi decoding is performed once more for a globaliteration (turbo equalization). It would be desirable to develop systemsthat perform this operation.

BRIEF DESCRIPTION OF THE DRAWINGS

Various embodiments of the invention are disclosed in the followingdetailed description and the accompanying drawings.

FIG. 1 is a diagram showing an embodiment of an error correction system.

FIG. 2 is a diagram showing an embodiment of an error correction systemshown at a first point in time.

FIG. 3 is a diagram showing an embodiment of an error correction systemshown at a second point in time.

FIG. 4 is a diagram showing an embodiment of an error correction systemshown at a third point in time.

FIG. 5 is a diagram showing an embodiment of an error correction systemshown at a fourth point in time.

FIG. 6 is a diagram showing an embodiment of an error correction systemshown at a fifth point in time.

FIG. 7 is a flowchart illustrating an embodiment of ADC memoryprocessing.

FIG. 8 is a flowchart illustrating an embodiment of Viterbi decoderprocessing.

FIG. 9 is a flowchart illustrating an embodiment of LLR memoryprocessing.

FIG. 10 is a flowchart illustrating an embodiment of LDPC decoderprocessing.

FIG. 11 is a diagram showing an embodiment of a decoding system with ashared soft output Viterbi algorithm (SOVA) with two LLR-LDPC processingpaths.

FIG. 12 is a diagram showing an example of some other system which doesnot use a shared SOVA.

FIG. 13 is a diagram showing an embodiment of a system with a sharedSOVA.

DETAILED DESCRIPTION

The invention can be implemented in numerous ways, including as aprocess; an apparatus; a system; a composition of matter; a computerprogram product embodied on a computer readable storage medium; and/or aprocessor, such as a processor configured to execute instructions storedon and/or provided by a memory coupled to the processor. In thisspecification, these implementations, or any other form that theinvention may take, may be referred to as techniques. In general, theorder of the steps of disclosed processes may be altered within thescope of the invention. Unless stated otherwise, a component such as aprocessor or a memory described as being configured to perform a taskmay be implemented as a general component that is temporarily configuredto perform the task at a given time or a specific component that ismanufactured to perform the task. As used herein, the term ‘processor’refers to one or more devices, circuits, and/or processing coresconfigured to process data, such as computer program instructions.

A detailed description of one or more embodiments of the invention isprovided below along with accompanying figures that illustrate theprinciples of the invention. The invention is described in connectionwith such embodiments, but the invention is not limited to anyembodiment. The scope of the invention is limited only by the claims andthe invention encompasses numerous alternatives, modifications andequivalents. Numerous specific details are set forth in the followingdescription in order to provide a thorough understanding of theinvention. These details are provided for the purpose of example and theinvention may be practiced according to the claims without some or allof these specific details. For the purpose of clarity, technicalmaterial that is known in the technical fields related to the inventionhas not been described in detail so that the invention is notunnecessarily obscured.

FIG. 1 is a diagram showing an embodiment of an error correction system.In the example shown, the decoding system shown in FIG. 1 is part of astorage system such as a disk storage system. Stored information isretrieved from disk media by analog-to-digital converter 102, followedby a Front-end DSP 100 which outputs ADC data.

The ADC data output by Front-end DSP 100 is passed to error correctiondecoder 104 which includes ADC memory 106. ADC memory 106 is configuredto buffer ADC data from Front-end DSP 100 in the event Viterbi decoder110 is occupied. In some embodiments, Viterbi decoder 100 is a softoutput Viterbi decoder. In this example, ADC memory 106 operates in afirst-in, first-out (FIFO) manner. If Viterbi decoder 110 is notoccupied and no higher-priority data needs to be decoded, ADC datapasses directly through ADC memory 106 to Viterbi decoder 110.

Viterbi decoder 110 is configured to process ADC data (via ADC memory104) or the output of LDPC decoder 114 in the event the LDPC decoderfails. Viterbi decoder 110 may be configured to operate in FIFO manner.For example, if the output of LDPC decoder 114 is completely availableearlier than ADC data from ADC memory 106, the output of LDPC decoder114 will be processed by Viterbi decoder 110. In some embodiments,Viterbi decoder 110 may be configured to give higher priority to processthe output of LDPC decoder 114 in the event the LDPC decoder fails andthat a retry is needed. The decision of using FIFO or giving higherpriority to retry may be related to system requirement. The retry withhigher priority scheme will be used as an example in this document.

The output of Viterbi decoder 110 is passed to block 113 which includeslog-likelihood ratio (LLR) memory 112. Although this example shows LLRmemory 112 followed by LDPC decoder 114 in block 113, LLR memory 112 innot necessary and in some embodiments is not included. Similarly,although some other examples described herein may include a memorybefore an LDPC decoder, it is not necessary to include such a memory. Insome embodiments, LLR memory 112 is included to improve a processingtime. If LDPC decoder 114 is not busy and there is no higher priorityinformation buffered in LLR memory 112, the output of Viterbi decoder110 may pass directly through LLR memory and be processed by LDPCdecoder 114. LLR memory 112 is used to buffer outputs from Viterbidecoder 110 in the event LDPC decoder 114 is occupied. LLR memory 112 isalso configured to store extrinsic reliability information from LDPCdecoder 114 in the event the LDPC decoder fails and a sector (or other“chunk” of information being processed) is retried. LLR memory 112 isconfigured to operate as a FIFO on the output data of Viterbi decoder110 which are to be processed by LDPC decoder 114, regardless the databeing processed for the first time or not.

More generally, block 113 is an iterative ECC (i.e., an error correcting(de)coder that operates iteratively). In this particular example, block113 is shown as an LLR memory and an LDPC decoder. In some otherembodiments, an iterative ECC includes an LDCP decoder and no memory.

LDPC decoder 114 can have two outcomes after processing concludes:decoding succeeds or fails. If decoding is successful, the output ofLDPC decoder 114 is output from error correction decoder 104 as decodeddata. If decoding fails, the system may decide to retry decoding. Insome embodiments, a retry is performed if the number of failures forthat sector (or some other “chunk” of information being processed) doesnot exceed a maximum number of failures. If a retry occurs, extrinsicreliability information is passed from LDPC decoder 114 to LLR memory112 for storage. In this example, to ensure that there is availablespace in LLR memory 112 for extrinsic reliability in the event of aretry, LLR memory 112 is configured to reserve space while LDPCprocessing is being performed for a given sector. In such embodiments,if LDPC decoding is successful, LLR memory 112 is informed it canrelease the reservation and can use the reserved space to store otherinformation. If the decoding is unsuccessful, the extrinsic reliabilityis stored in the reserved space.

If a retry is attempted, the output of LDPC decoder 114 is passed backto Viterbi decoder 110 for global iteration (turbo equalization). Inthis example, the output of LDPC decoder 114 is passed to LLR memory 112first, and eventually is passed back to Viterbi decoder 110. Viterbidecoder 110 operates in FIFO to choose data between ADC data from ADCmemory and the output of LDPC decoder 114 as retry. Once Viterbi decoder110 has completing processing of the retry, the output is passed to LLRmemory and is passed to LDPC decoder 114 for another decoding attempt.

While Viterbi decoder 110 is processing a retry, LDPC decoder 114 inthis example is free and processes any Viterbi decoded data stored inLLR memory 112. LLR memory 112 operates in a FIFO manner and outputs thesector waiting the longest time to be processed by LDPC decoder 114.

FIG. 2 is a diagram showing an embodiment of an error correction systemshown at a first point in time. In the example shown, the errorcorrection system of FIG. 1 is shown with example data passing throughthe system. In this and other figures described below, ADC data outputby Front-end DSP 100 is output in the order D0, D1, D2, . . . . That is,D0 is the first piece of data (e.g., a sector) output, D1 is the secondpiece of data output, etc.

At the point in time shown here, D0 is being processed by Viterbidecoder 110. Since Viterbi decoder 110 is busy processing D0, D1 isstored in ADC memory 106 until Viterbi decoder 110 is free.

FIG. 3 is a diagram showing an embodiment of an error correction systemshown at a second point in time. In the example shown, Viterbi decoder110 is processing D1 and ADC memory 106 is storing D2 and D3. D0 isbeing processed by LDPC decoder 114 but will fail LDPC decoding.

FIG. 4 is a diagram showing an embodiment of an error correction systemshown at a third point in time. After failing LDPC decoding, extrinsicreliability information for D0 is stored in LLR memory 112 at slot 112a. In the example shown, LLR memory 112 includes four slots. In someother embodiments, the number of slots varies (e.g., based on theprocessing time of LDPC decoder 114, the processing time of Viterbidecoder 110, the arrival rate of ADC data, and/or the number of retriespermitted). In some embodiments, the size of LLR memory 112 and/or ADCmemory 106 is determined via simulation. For example, a simulation maybe set up where ADC data arrives at a certain arrival rate, the ADC datacontains an expected or maximum amount of noise, there are a maximumnumber of retries for a given sector, and LDPC decoder and Viterbidecoder take a certain amount of processing time.

In the example, assuming Viterbi decoder 110 is configured to givehigher priority to the output of LDPC decoder 114 in case a retry isdecided. Although D2 and D3 were stored in ADC memory 106 waiting to beprocessed by Viterbi decoder 110 (see FIG. 3), the retry of D0 hashigher priority and D2 and D3 are remain in ADC memory 106 and Viterbidecoder 110 processes the retry of D0. In this example, the retry of D0is indicated as D0′. If Viterbi decoder 110 is configured to operate inFIFO manner, the Viterbi decoder 110 will process the sector in thisorder: D2, D3 and the retry of D0.

In the example shown, a slot is reserved for the data being processed byLDPC decoder 114 in the event decoding for that piece of data fails. Inthis example, slot 112 b is reserved for D1 which is currently beingprocessed by LDPC decoder 114.

In this example, Viterbi decoder 110 is configured to give a highpriority to the LDPC data being retried as opposed to data from ADCmemory 106. In some embodiments, Viterbi decoder 110 is configured tooperate in a First In, First Out (FIFO) manner where data is operated onin the order in which it arrived. In some embodiments, a system isconfigurable so that a Viterbi decoder operates in a FIFO manner oralternatively prioritizes data (e.g., as specified by a user).

FIG. 5 is a diagram showing an embodiment of an error correction systemshown at a fourth point in time. In the example shown, D1 hassuccessfully completed LDPC decoding and is output as decoded data byerror correction decoder 104. The reservation of slot 112 b for D1 (seeFIG. 4) is released since LDPC decoding completed successfully for thatpiece of data.

The retry of D0 (i.e., D0′) has completed Viterbi decoding and theoutput of Viterbi decoder 110 for D0 stored in LLR memory 112 (see slot112 a in FIG. 4) are passed to LDPC decoder 114 for processing. Slot 112a is reserved for (the retry of) D0 in case LDPC processing fails again.In some embodiments, if D0 fails LDPC decoding for a certain number oftimes, the system declares an error for that sector.

D2 is the oldest piece of data that was stored in ADC memory 106 and isprocessed by Viterbi decoder 110. Since no retry was pending, Viterbidecoder 110 processed the next piece of ADC data stored in ADC memory106 in a FIFO manner.

FIG. 6 is a diagram showing an embodiment of an error correction systemshown at a fifth point in time. In the example shown, the retry of D0successfully completed LDPC decoding and is output as decoded data. Asshown in this example, decoded data can (in some cases) be output out oforder (e.g., D1 was output as decoded data before D0).

LDPC decoder 114 is processing D2 and slot 112 a in LLR memory 112 isreserved for D2. Since LDPC decoder 114 is occupied processing D2 butViterbi processing for D3 has completed, the Viterbi output for D3 isstored in slot 112 b in LLR memory 112. Viterbi decoder 110 isprocessing D4 and ADC memory 106 is storing D5 and D6 until they can beprocessed by Viterbi decoder 110.

FIG. 7 is a flowchart illustrating an embodiment of ADC memoryprocessing. In the example shown, the processing is performed by ADCmemory 106 in FIG. 1. At 700, it is determined if data is received froman ADC. For example, in some embodiments Front-end DSP 100 and errorcorrection decoder 104 are implemented on different application-specificintegrated circuits (ASICs) or field-programmable gate arrays (FPGAs)and an ADC memory may not necessarily know or control when data isreceived.

If data is received, the ADC data is stored in ADC memory at 702. Afterstoring data at 702 or if no data is received, it is determined at 704if a Viterbi decoder is free and there is no retry. For example, in FIG.4, the retry of D0 has priority over D2 and D3 at Viterbi decoder 110.If the Viterbi is free and there is no retry, ADC data stored in memoryis output at 706. In this example, data is output by the ADC memory in aFIFO manner. After outputting data at 706 or the Viterbi is not freeand/or there is a retry, it is determined at 708 if the process is done.If not, the process determines at 700 is data is received.

FIG. 8 is a flowchart illustrating an embodiment of Viterbi decoderprocessing. In the example shown, the processing is performed by Viterbidecoder 110 in FIG. 1. At 800, it is determined if a retry is waiting.For example, in FIG. 4 data D0 needs to be retried, whereas in FIG. 5there is no retry waiting and data D2 is processed. If there is a retry,data that failed LDPC decoding is processed at 802. Otherwise, ADC datais processed at 804. Referring back to the example of FIG. 1, the selectsignal (not shown) of multiplexer 108 controls whether processing atstep 802 or 804 is performed.

After processing at 802 or 804, it is determined at 806 whether theprocess is done. If not, it is determined at 800 if a retry is waiting.

FIG. 9 is a flowchart illustrating an embodiment of LLR memoryprocessing. In the example shown, the processing is performed by LLRmemory 112 in FIG. 1. At 900, it is determined if data is received froma Viterbi decoder. If so, the Viterbi data is stored in the LLR memoryat 902. For example, in FIG. 6, slot 112 b is used to store the Viterbioutput for D3. After storing at 902 or if there is no data received, itis determined if the LDPC decoder is free at 904. If so, data stored inthe LLR memory is output at 906. Retries are output first, thennon-retries in a FIFO manner. A slot is reserved at 908. For example, inFIG. 6, while D2 is being processed by LDPC decoder 114, slot 112 b isreserved for D2 in the event D2 fails LDPC decoding and space isrequired for extrinsic reliability associated with D2 to be stored.

If the LDPC is busy at 904 or after reserving a slot at 908, it isdetermined if the LDPC was successful at 910. If so, the reservation isreleased at 914, otherwise the extrinsic reliability is stored in thereserved slot at 912. After releasing the slot at 914 or after storingextrinsic reliability at 912, it is determined if the process is done.If not, it is determined if data has been received from the Viterbidecoder at 900.

FIG. 10 is a flowchart illustrating an embodiment of LDPC decoderprocessing. In the example shown, the processing is performed by LDPCdecoder 114 in FIG. 1. At 1000, it is determined if a retry is waiting.If so, Viterbi data for a retry is processed at 1002, otherwise Viterbidata for a non-retry is processed at 1004. After processing at 1002 or1004, it is determined at 1006 if the LDPC was successful. If so,decoded data is output and the LLR memory reservation is released at1008. See, e.g., FIGS. 4 and 5 where D1 is output as decoded data andthe reservation of slot 112 b is released. If LDPC decoding fails, it isdetermined if a maximum number of failures has been exceeded at 1010. Ifso, a failure is signaled for a sector and a LLR reservation is releasedat 1012. If not, a retry for sector is signaled and the reliability iswritten to the LLR memory at 1014. After processing at 1008, 1012, or1014, it is determined if the process is done. If not, it is determinedat 1000 if a retry is waiting.

FIG. 11 is a diagram showing an embodiment of a decoding system with ashared soft output Viterbi algorithm (SOVA) with two LLR-LDPC processingpaths. In the example shown, decoder 1150 shows one embodiment of ashared SOVA system that can be used to replace decoder 1100. Decoder1100 includes processing paths 1102, 1104, and 1106. Processing paths1102 is used to decode data received from Front-end DSP by passing itthrough SOVA 1102 a, LLR 1102 b, and LDPC 1102 c. If decoding failsafter processing by processing path 1102, processing path 1104 (whichincludes SOVA 1104 a, LLR 1104 b, and LDPC 1104 c) attempts to decodethe data. If decoding by processing path 1104 fails, then processingpath 1106 (which includes SOVA 1106 a, LLR 1106 b, and LDPC 1106 c)attempts to decode the data. In this example, if decoder 1150 is unableto properly decode the data after three processing attempts (e.g.,corresponding to processing paths 1102, 1104, and 1106), the decoderstops trying to decode that data.

Decoder 1150 includes a single SOVA (1152). SOVA 1152 is shared byprocessing paths 1154 (which includes LLR 1154 a and LDPC 1154 b) and1156 (which includes LLR 1156 a and LDPC 1156 b). Processing path 1154is configured to perform a first or initial processing of data receivedfrom SOVA 1152. If processing path 1154 is unable to properly decode thedata, processing path 1156 attempts to decode the data. In variousembodiments, processing path 1156 is configured to attempt multipledecodes of a given piece of data. For example, if processing path 1156fails to decode data it may be configured to attempt decoding again. Insome embodiments, processing path 1156 is configured to attempt decodingup to N times, where N is a configurable or programmable number.

In this particular example, decoder 1150 (with a single shared SOVA) isused in place of a decoder with 3 SOVAs/processing paths). In some otherembodiments, a system with a shared SOVA (e.g., decoder 1150) may beused in place of a system with any number of SOVAs and/or processingpaths.

Decoder 1100 and 1150 perform the same function but some lower levelcharacteristics may not necessarily be the same between the two. In somecases for example, the order in which decoded data is output may varybetween decoder 1100 and 1150. For example, decoder 1100 may output datain order whereas decoder 1150 may output data out of order. In anotherexample, the latency or processing time associated with decoders 1100and 1150 may not necessarily be the same. One decoder may have a longerprocessing time or delay from start to finish compared to the other.

FIG. 12 is a diagram showing an example of some other system which doesnot use a shared SOVA. In the example shown, SOVA 1201 in Front-endportion 1200 is not shared and another SOVA (i.e., SOVA 1204) isrequired in ECC 1203. LLR memory 1202 in ECC 1203 is required in thissystem because SOVA 1201 outputs data continuous and LLR memory 1202 isrequired to buffer this data, otherwise data will be lost since LDPCprocessing time can vary. ADC memory 1205 is required for SOVA 1204.

A typical ECC system is shown in FIG. 12, where ADC data is sent to aSOVA (or Viterbi decoder) directly. Reliability data is pre-computed andstored in an LLR memory which is to be used by LDPC decoder. ExtrinsicLLR data of the LDPC decoder is sent to another SOVA within the ECCsystem for global iteration (turbo equalization).

The number of sectors buffered in memory is dependent upon the LDPCdecoding latency. However, both the ADC and LLR data of each sector mustbe buffered in this scheme.

What is disclosed herein (in at least some embodiments) is to buffer anADC memory before SOVA processing as shown in the next figure. Usingthis scheme, only ADC data is buffered during LDPC decoding. LLR iscomputed when needed. In some embodiments, LLR is buffered to compensatefor the SOVA latency so that the LDPC decoder can be utilized moreefficiently. What is also disclosed herein (in at least someembodiments) is to share the SOVA such that the shared SOVA can processdata from both the channel and the LDPC decoder in a multiplexed manner.In contrast, the SOVAs in FIG. 12 can only process data from a singlesource (i.e., only the channel or only the LDPC decoder but not both).An example of the above techniques is show in the figure below.

FIG. 13 is a diagram showing an embodiment of a system with a sharedSOVA. In the example shown, the purpose or function performed by ADCmemory 1302 is different than that of ADC memory 1205 in FIG. 12.Whereas ADC memory 1302 buffers ADC data for all iterations orrepetitions of SOVA processing (including a first or initial pass), ADCmemory 1205 is used for second and later iterations of SOVA processing(e.g., if decoding fails during a first or initial pass). LLR memory1303 is not required and in some embodiments LLR memory 1303 is notincluded. SOVA 1301 only executes when need (e.g., when block 1300 isidle or is able to accept SOVA output). In some embodiments, althoughnot required, LLR memory 1303 is included in block 1300 to improvespeed. The size of 1303 is at least in some embodiments much smallerthan LLR memory 1202 in FIG. 12.

Although the foregoing embodiments have been described in some detailfor purposes of clarity of understanding, the invention is not limitedto the details provided. There are many alternative ways of implementingthe invention. The disclosed embodiments are illustrative and notrestrictive.

What is claimed is:
 1. A system for decoding information, comprising: afirst error correction decoder configured to: perform error correctiondecoding on input data to obtain first decoded data; and in the eventerror correction decoding by a second error correction decoder on thefirst decoded data fails, perform error correction decoding using anoutput of the second error correction decoder; the second errorcorrection decoder configured to: perform the error correction decodingon the first decoded data; and send, to a memory, a reservation requestprior to completion of the error correction decoding on the firstdecoded data; and the memory, wherein the memory is configured toreserve space in the memory in response to receiving the reservationrequest from the second error correction decoder.
 2. The system of claim1, wherein the first error correction decoder includes a Viterbidecoder.
 3. The system of claim 1, wherein the second error correctiondecoder includes a low-density parity-check (LDPC) decoder.
 4. Thesystem of claim 1, wherein the memory is further configured to store thefirst decoded data in the event the second error correction decoder isoccupied when the first decoded data is output by the first errorcorrection decoder.
 5. The system of claim 1, further comprising asecond memory configured to store the input data in the event the firsterror correction decoder is occupied when the input data is received. 6.The system of claim 1, wherein the second error correction decoder isfurther configured to: in the event error correction decoding on thefirst decoded data is successful, send, to the memory, a messageassociated with releasing the reservation.
 7. The system of claim 6,wherein the second error correction decoder is further configured to: inthe event error correction decoding on the first decoded data isunsuccessful, send the output of the second error correction decoder,used by the first error correction decoder, to the memory for storage ina space reserved by the reservation request.
 8. A method for decodinginformation, comprising: performing error correction decoding on inputdata to obtain first decoded data using a first error correctiondecoder; in the event error correction decoding by a second errorcorrection decoder on the first decoded data fails, performing errorcorrection decoding using an output of the second error correctiondecoder and using the first error correction decoder; performing theerror correction decoding on the first decoded data using the seconderror correction decoder; sending, from the second error correctiondecoder to a memory, a reservation request prior to completion of theerror correction decoding on the first decoded data; and reservingspace, in the memory, in response to receiving the reservation requestfrom the second error correction decoder.
 9. The method of claim 8,wherein the method is performed using one or more of the following: anapplication-specific integrated circuit (ASIC) or a field-programmablegate array (FPGA).
 10. The method of claim 8, wherein the first errorcorrection decoder includes a Viterbi decoder.
 11. The method of claim8, wherein the second error correction decoder includes a low-densityparity-check (LDPC) decoder.
 12. The method of claim 8, furthercomprising storing, at the memory, the first decoded data in the eventthe second error correction decoder is occupied when the first decodeddata is output by the first error correction decoder.
 13. The method ofclaim 8, further comprising storing, at a second memory, the input datain the event the first error correction decoder is occupied when theinput data is received.
 14. The method of claim 8, further comprising inthe event error correction decoding on the first decoded data issuccessful, sending, from the second error correction decoder to thememory, a message associated with releasing the reservation.
 15. Themethod of claim 14, further comprising in the event error correctiondecoding on the first decoded data is unsuccessful, sending the outputof the second error correction decoder, used by the first errorcorrection decoder, from the second error correction decoder to thememory for storage in a space reserved by the reservation request.
 16. Acomputer program product for decoding information, the computer programproduct being embodied in a tangible, non-transitory computer readablestorage medium and comprising computer instructions for: performingerror correction decoding on input data to obtain first decoded datausing a first error correction decoder; in the event error correctiondecoding by a second error correction decoder on the first decoded datafails, performing error correction decoding using an output of thesecond error correction decoder and using the first error correctiondecoder; performing the error correction decoding on the first decodeddata using the second error correction decoder; sending, from the seconderror correction decoder to a memory, a reservation request prior tocompletion of the error correction decoding on the first decoded data;and reserving space, in the memory, in response to receiving thereservation request from the second error correction decoder.
 17. Thecomputer program product of claim 16, wherein the first error correctiondecoder includes a Viterbi decoder.
 18. The computer program product ofclaim 16, wherein the second error correction decoder includes alow-density parity-check (LDPC) decoder.
 19. The computer programproduct of claim 16, further comprising computer instructions forstoring, at the memory, the first decoded data in the event the seconderror correction decoder is occupied when the first decoded data isoutput by the first error correction decoder.
 20. The computer programproduct of claim 16, further comprising computer instructions forstoring, at a second memory, the input data in the event the first errorcorrection decoder is occupied when the input data is received.
 21. Thecomputer program product of claim 16, further comprising computerinstructions for in the event error correction decoding on the firstdecoded data is successful, sending, from the second error correctiondecoder to the memory, a message associated with releasing thereservation.
 22. The computer program product of claim 21, furthercomprising computer instructions for in the event error correctiondecoding on the first decoded data is unsuccessful, sending the outputof the second error correction decoder, used by the first errorcorrection decoder, from the second error correction decoder to thememory for storage in a space reserved by the reservation request.